This invention relates generally to manufacturing processes for fabricating semiconductor integrated devices. More particularly, it relates to an improved method of forming circuit structures having linewidths which are smaller than what is achievable by conventional UV lithographic technology on ultra-thin resist layers.
As is generally known to those in the semiconductor industries, there is a continuing trend of manufacturing semiconductor integrated circuits with higher and higher densities on a smaller chip area. As a consequence of this desire for large scale integration, this has led to a continued shrinking of the circuit dimensions and features of the devices so as to reduce manufacturing costs and to improve circuit functionality. The ability to reduce the size structures such as shorter gate lengths in field-effect transistors is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. Currently, optical steppers expose the photoresist using light having a wavelength of 248 nm is widely used in manufacturing, but a radiation having a wavelength of 193 nm is being experimented in research and development laboratories. Further, the next generation lithographic technologies will in all likelihood progress toward a radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Extreme Ultra-Violet (EUV) lithography (≈13 nm).
As the wavelength of the radiation decreases, such classic image exposure techniques cannot be used to satisfactorily generate the pattern linewidths in the photoresist of less than 0.25 xcexcm (2500 xc3x85). This is due to the fact that the organic-based photoresist materials will become increasingly opaque to the radiation. In order to overcome this drawback, there has been developed in recent years of using ultra-thin resist (UTR) coatings in order to maintain the desired characteristics of the masked photoresist structures (e.g., near vertical sidewalls for the resist profiles, maximum exposure/focus latitude). In the current state-of-the-art, integrated circuit manufacturers have been using in the resist process a resist coating having a standard photoresist thickness of more than 0.5 xcexcm (5,000 xc3x85) for 248 nm lithography and 0.4 xcexcm (4,000 xc3x85) for 193 nm lithography. Thus, a resist coating having an UTR thickness is considered to be resist films of less than 0.25 xcexcm (2500 xc3x85) in thickness.
However, the use of UTR coating is not without any problems. The use of UTR coating suffer from the disadvantage that during the etch process the films being etched often do not scale down as rapidly as the thickness of the resist coating. In addition, even when such films can be scaled down or the selectivity of the etch process can be improved, the increasing use of trim (controlled line width reduction) process can fully consume the etch process margin for the underlying film. Thus, it has been recognized that a major problem to date of using UTR coating is related to etching underlying films when used with trim processes.
Accordingly, there is still a need of providing a fabrication process for forming circuit structures smaller than the capability of the lithographic technology while using ultra-thin resist processes. This is achieved in the present invention by utilizing a hardmask which is patterned using resist and is then trimmed so as to reduce the linewidth of the hardmask before etching the underlying film.
Accordingly, it is a general object of the present invention to provide an improved method of forming circuit structures having linewidths which are smaller than what is achievable by conventional UV lithographic technology on ultra-thin resist layers.
In accordance with a preferred embodiment of the present invention, there is provided an improved method of forming circuit structures having linewidths which are smaller than the capabilities of typical UV lithographic techniques on ultra-thin resist layers. A semiconductor wafer stack is provided which is formed of a substrate and a gate conductive layer above the substrate. A hardmask layer is deposited over the gate conductive layer. An ultra-thin resist layer is then deposited over the hardmask layer.
A resist mask is formed which has an initial linewidth. The hardmask layer is isotropically over-etched to form a hardmask having a final linewidth which is narrower than the initial linewidth of the resist mask and corresponds to a desired gate linewidth. The gate conductive layer as defined by the hardmask is anisotopically etched to form a gate having a width substantially equal to the final linewidth of the hardmask.